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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13704-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90590 Series
MB90594/591/F594A/F591/V590A
s DESCRIPTION
The MB90590-series with two FULL-CAN interfaces and FLASH ROM is especially designed for automotive and industrial applications. Its main feature are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.5m CMOS technology, Fujitsu now also offers on-chip FLASH-ROM program memory. An internal voltage booster removes the necessity for a second programming voltage. An on board voltage regulator provides 3V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 62.5 nsec instruction cycle time from an external 4 MHz clock. The unit features 4 Stepper Motor Controllers with high current outputs. Furthermore it features a 6 channel Output Compare Unit and a 6 channel Input Capture Unit with a 16-bit free running timer. Three UARTs constitute additional functionality for communication purposes.
s FEATURES
* * * * 16-bit core CPU:4MHz external clock (16 MHz internal, 62.5 nsec instr. cycle time) New 0.5 m CMOS Process Technology Internal voltage regulator supports 3V MCU core, offering low EMI and low power consumption figures Two FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) * Powerful interrupt functions (8 progr. priority levels; 8 external interrupts) (Continued)
s PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
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MB90590 Series
(Continued) * EI2OS - Automatic transfer function indep.of CPU; 16 ch. of intelligent I/O Services * 18-bit Time-base counter * Watchdog Timer * 3 full duplex UARTs; support 10.4 KBaud (USA standard ) * Serial I/O: 1ch for synchronous data transfer * A/D Converter: 8 ch. analog inputs (Resolution 10 bits or 8 bits) * 16-bit reload timer 2ch * ICU (Input capture) 16bit * 6ch * OCU (Output capture) 16bit * 6ch * 16-bit Programmable Pulse Generator 6ch * Stepping Motor Controller 4ch * Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) * 4-byte instruction execution queue * signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available * Program Patch Function * Fast Interrupt processing * Low Power Consumption - 7 different power saving modes: (Sleep, Stop, CPU intermittent mode, Hardware standby,...) * Sound Generator * Real Time Watch Timer * Package: 100-pin plastic QFP
Controller Area Network (CAN) - License of Robert Bosch GmbH
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MB90590 Series
s PRODUCT LINEUP
The following table provides a quick outlook of the MB90590 Series Features MB90V590A MB90F594A/MB90F591 CPU System clock F MC-16LX CPU On-chip PLL clock multiplier ( x 1, x 2, x 3, x 4, 1/2 when PLL stop) Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x 4) External 6 Kbytes 0.5 m CMOS with onchip voltage regulator for internal power supply Boot-block Flash memory 256/384 Kbytes Hard-wired reset vector 6/8 Kbytes Mask ROM 256/384 Kbytes 6/8 Kbytes
2
MB90594/MB90591
ROM RAM
Technology
0.5 m CMOS with on-chip voltage regulator for internal power supply + Flash 0.5 m CMOS with onmemory with chip voltage regulator for On-chip charge pump for programming internal power supply voltage
Operating voltage range Temperature range Package UART (3 channels) PGA-256
5 V 10% (Target for MB90F591 and MB90591) - 40 to 85 C QFP-100
Full duplex double buffer Supports asynchronous/synchronous (with start/stop bit) transfer Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000bps (asynchronous) 500K/1M/2Mbps (synchronous) at System clock = 16MHz Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25K/62.5K/125K/500K/1Mbps at System clock = 16MHz 10-bit or 8-bit resolution 8 input channels Conversion time: 26.3s (per one channel) Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Directly operates with the oscillation clock Facility to correct oscillation deviation Read/Write accessible Second/Minute/Hour registers Signals interrupts Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare(Channel 0) Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28(fsys = System clock freq.) Signals an interrupt when a match with 16-bit IO Timer Six 16-bit compare registers A pair of compare registers can be used to generate an output signal
Serial IO
A/D Converter 16-bit Reload Timer (2 channels)
Watch Timer
16-bit IO Timer 16-bit Output Compare (6 channels)
(Continued)
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MB90590 Series
(Continued) Features
16-bit Input Capture (6 channels)
MB90V590A
MB90F594A/MB90F591
MB90594/MB90591
Rising edge, falling edge or rising & falling edge sensitive Six 16-bit Capture registers Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes Twelve 8-bit reload counters Twelve 8-bit reload registers for L pulse width 8/16-bit Twelve 8-bit reload registers for H pulse width Programma-ble A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as Pulse Gen-erator 8-bit prescaler plus 8-bit reload counter (6channels) 6 output pins Operation clock freq.: fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128s@fosc=4MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps Four high current outputs for each channel Synchronized two 8-bit PWM's for each channel Succeeds to MB89940 design resource
CAN Interface (2 channels)
Stepper Motor Controller (4 channels)
External Inter-rupt Can be programmed edge sensitive or level sensitive (8 channels) 8-bit PWM signal is mixed with tone frequency from 8-bit reload counter Sound Gener-ator PWM frequency : 62.5K, 31.2K, 15.6K, 7.8KHz at System clock = 16MHz Tone frequency : PWM frequency / 2 / (reload value + 1) IO Ports Virtually all external pins can be used as general purpose IO All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Supports automatic programming,Embedded Algorithm TM * Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles: 10,000 times Data retention time: 10 years Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Flash Writer from Minato Electronics Inc. Boot block configuration Erase can be performed on each block Block protection with external programming voltage
Flash Memory
*: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. 4
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MB90590 Series
s PIN ASSIGNMENT
(Top view)
P13/OUT5 P12/OUT4 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P16/SGO P17/SGA P15/TX1 P14/RX1 P04/IN4 P03/IN3 P02/IN2 P01/IN1 P05/IN5 P00/IN0
Vcc
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
X0
P20 P21 P22 P23 P24/INT4 P25/INT5 P26/INT6 P27/INT7 P30 P31 Vss P32 P33 P34/SOT0
P35/SCK0 P36/SIN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Vss
X1
P95/INT3 P94/INT2 P93/INT1 RST P92/INT0 P91/RX0 P90/TX0 DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS HST MD2
P37/SIN1 P40/SCK1 P41/SOT1 P42/SOT2 P43/SCK2 P44/SIN2 Vcc P45/SCIN3 P46/SCK3 P47/SOT3 C P50/PPG0 P51/PPG1 P52/PPG2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 P57/TOT/WOT
49 MD0
P55/PPG5/ADTG
P60/AN0
P61/AN1
P62/AN2
P63/AN3
Vss
P64/AN4
P54/PPG4
P65/AN5
AVR+
AVR-
AVcc
AVss
P66/AN6
P67/AN7
P56/TIN
P53/PPG3
(FPT-100P-M06)
MD1
50
5
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MB90590 Series
s PIN DESCRIPTION
No. 82 83 77 52 85 to 90 Pin name X0 X1 RST HST P00 to P05 IN0 to IN5 P06 to P07 P10 to P13 91 to 96 OUT0 to OUT5 P14 RX1 P15 98 TX1 P16 99 SGO P17 100 SGA P20 to P23 P24 to P27 INT4 to INT7 P30 to P31 P32 to P33 P34 14 SOT0 P35 15 SCK0 D D D D D D Circuit type A B C D Oscillation input Oscillation output Reset input Hardware standby input General purpose IO Inputs for the Input Captures General purpose IO Outputs for the Output Compares. To enable the signal outputs, the corresponding bits of the Port Direction registers should be set to "1". General purpose IO RX input for CAN Interface 1 General purpose IO TX output for CAN Interface 1. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO SGO output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO SGA output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO General purpose IO External interrupt input for INT4 to INT7 General purpose IO General purpose IO General purpose IO SOT output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". General purpose IO SCK input/output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to "1". Function
97
D
1 to 4 5 to 8 9 to 10 12 to 13
D D D D
(Continued)
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MB90590 Series
No. 16 17 18 19 20 21 22 24 25 26
Pin name P36 SIN0 P37 SIN1 P40 SCK1 P41 SOT1 P42 SOT2 P43 SCK2 P44 SIN2 P45 SIN3 P46 SCK3 P47 SOT3 P50 to P55 PPG0 to PPG5, ADTG P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P56 TIN P57
Circuit type D D D D D D D D D D General purpose IO SIN input for UART 0 General purpose IO SIN input for UART 1 General purpose IO SCK input/output for UART 1 General purpose IO SOT output for UART 1 General purpose IO SOT output for UART 2 General purpose IO SCK input/output for UART 2 General purpose IO SIN input for UART 2 General purpose IO SIN input for the Serial IO General purpose IO
Function
SCK input/output for the Serial IO General purpose IO SOT output for the Serial IO General purpose IO Outputs for the Programmable Pulse Generators. Pin number 33 is also shared with ADTG input for the external trigger of the A/D Converter. General purpose IO Inputs for the A/D Converter General purpose IO Inputs for the A/D Converter General purpose IO TIN input for the 16-bit Reload Timers General purpose IO TOT output for the 16-bit Reload Timers and WOT output for the Watch Timer. Only one of three output enable flags in these pheripheral blocks can be set at a time. Otherwise the output signal has no meaning.
28 to 33
D
38 to 41 43 to 46 47
E E D
48
TOT/WOT
D
(Continued)
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MB90590 Series
(Continued) No.
Pin name P70 to P73 PWM1P0 PWM1M0 PWM2P0 PWM2M0 P74 to P77 PWM1P1 PWM1M1 PWM2P1 PWM2M1 P80 to P83 PWM1P2 PWM1M2 PWM2P2 PWM2M2 P84 to P87 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P90 TX0 P91 RX0 P92 INT0 P93 INT1 P94 INT2 P95 INT3 DVCC
Circuit type General purpose IO F
Function
54 to 57
Output for Stepping Motor Controller channel 0.
General purpose IO F
59 to 62
Output for Stepping Motor Controller channel 1.
General purpose IO F
64 to 67
Output for Stepping Motor Controller channel 2.
General purpose IO F
69 to 72
Output for Stepping Motor Controller channel 3.
74 75 76 78 79 80 58 68 53 63 73
D D D D D D
General purpose IO TX output for CAN Interface 0 General purpose IO RX input for CAN Interface 0 General purpose IO External interrupt input for INT0 General purpose IO External interrupt input for INT1 General purpose IO External interrupt input for INT2 General purpose IO External interrupt input for INT3 Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) Dedicated ground pins for the high current output buffers (Pin No. 54 to 72)
DVSS
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MB90590 Series
s I/O CIRCUIT TYPE
Circuit Type X1 Circuit Remarks * Oscillation feedback resistor: 1 M approx.
X0 A
Standby control signal
* Hysteresis input with pull-up Resistor: 50 k approx. B R R HYS
* Hysteresis input C R HYS
VCC P-ch N-ch
* CMOS output * Hysteresis input
D
R
HYS
(Continued)
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MB90590 Series
Circuit Type
Circuit Vcc P-ch N-ch
Remarks * CMOS output * Hysteresis input * Analog input
E
Analog input R HYS
* CMOS high current output * Hysteresis input P-ch High current F N-ch
R
HYS
Vcc P-ch High current G N-ch
* CMOS high current output * Hysteresis input * Analog input
Analog input R HYS
(Continued)
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MB90590 Series
(Continued) Circuit Type
Circuit
Remarks * Hysteresis input with pull-down Resistor: 50 Kohm approx. * Flash version does not have pull-down register.
R H R
HYS
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MB90590 Series
s HANDLING DEVICES
(1)Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: * A voltage higher than Vcc or lower than Vss is applied to an input or output pin. * A voltage higher than the rated voltage is applied between Vcc and Vss. * The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. (2)Handling unused input pins Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pulldown resistor. (3)Using external clock To use external clock, drive the X0 and X1 pins in reverse phase. Below is a diagram of how to use external clock. MB90590 Series X0 X1
Using external clock (4)Power supply pins (Vcc/Vss) Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vsslevel power supply pins. (See the figure below.) If there are more than one Vcc or Vss system, the device may operate incorrectly even within the guaranteed operating range. Vcc Vss
Vcc Vss Vcc
Vss
MB90590 Series
Vcc Vss
Vss
Vcc
(5) Pull-up/down resistors The MB90590 Series does not support internal pull-up/down resistors. Use external components where needed. 12
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MB90590 Series
(6) Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. (7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply(AVCC, AVR + , AVR - ) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVR + or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). (8) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR + = VSS. (9) N.C. Pin The N.C. (internally connected) pin must be opened for use. (10) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more ms (0.2 V to 2.7 V). (11) Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. (12) Directions of "DIV A, Ri" and "DIVW A, RWi" instructions In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi"), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00h". If the values of the corresponding bank register (DTB,ADB,USB,SSB) are setting other than "00h", the remainder by the execution result of the instruction is not stored in the register of the instruction operand.
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MB90590 Series
s BLOCK DIAGRAM
X0,X1 RST HST
Clock Controller
16LX CPU
RAM 6/8 K
IO Timer Input Capture 6ch
IN[5:0]
ROM/Flash
256 K/384 K
Output Compare 4ch
OUT[5:0]
Prescaler x 3
SOT[2:0] SCK[2:0] SIN[2:0]
UART 3ch
8/16-bit PPG 6ch
PPG[5:0]
Prescaler
CAN 2ch
RX[1:0] TX[1:0]
SOT3 SCK3 SIN3 AVCC AVSS AN[7:0] AVR+ AVRADTG
Serial I/O PWM1M[3:0] PWM1P[3:0] FMC-16 Bus SMC 4ch PWM2M[3:0] PWM2P[3:0] DVCC[1:0] DVSS[2:0]
10-bit ADC 8ch
TIN TOT/WOT
16-bit Reload Timer 2ch
External Interrupt
INT[7:0]
Sound Generator
SGO SGA
Watch Timer
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MB90590 Series
s MEMORY SPACE
The memory space of the MB90590 Series is shown below
MB90V590A FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H MB90594/F594A ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H MB90591/F591 ROM (FF bank) ROM (FE bank) ROM (FD bank)
ROM (FB bank) ROM (FA bank) ROM (F9 bank)
00FFFFH 004000H
ROM (Image of FF bank)
00FFFFH 004000H
ROM (Image of FF bank)
00FFFFH 004000H
ROM (Image of FF bank)
0028FFH 002100H 0020FFH 001FFFH 001900H 0018FFH
RAM 2K
0028FFH 002100H 0020FFH 001FFFH 001900H 0018FFH Peripheral 001FFFH 001900H 0018FFH
RAM 2K
Peripheral
Peripheral
RAM 6K 000100H 0000BFH 000000H Peripheral 000100H 0000BFH 000000H
RAM 6K 000100H Peripheral 0000BFH 000000H
RAM 6K
Peripheral
Memory space map The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00. The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.
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MB90590 Series
s I/O MAP
Address 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 1A 1B 20 21 22 23 24 25 26 27
H H H H H H H H H H
Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Analog Input Enable Serial Mode Control 0 Status 0 Input/Output Data 0 Rate and Datar 0 Serial Mode Control 1 Status 1 Input/Output Data 1 Rate and Datar 1
Abbreviation Access PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 ADER UMC0 USR0 UIDR0/ UODR0 URD0 UMC1 USR1 UIDR1/ UODR1 URD1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Pripheral Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 6, A/D
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _ _ XXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B
0A to 0F H
H H H H H H H H H H H H
Reserved
Reserved Reserved
1C to 1F H
H H
UART0
H
XXXXXXXXB 0 0 0 0 0 0 0XB 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B
H H H
UART1
H
XXXXXXXXB 0 0 0 0 0 0 0XB
H
(Continued)
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MB90590 Series
Address 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47
H H
Register Serial Mode Control 2 Status 2 Input/Output Data 2 Rate and Datar 2 Serial Mode Control Serial Mode Control Serial Data Edge Selector External Interrupt Enable External Interrupt Request External Interrupt Level External Interrupt Level A/D Control Status 0 A/D Control Status 1 A/D Data 0 A/D Data 1
PPG0 operation mode control register PPG1 operation mode control register PPG0 and PPG1 clock select register
Abbreviation Access UMC2 USR2 UIDR2/ UODR2 URD2 SMCS SMCS SDR SES ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 PPGC2 PPGC3 PPG23 PPGC4 PPGC5 PPG45 PPGC6 PPGC7 PPG67 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral
Initial value 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B
UART2
H
XXXXXXXXB 0 0 0 0 0 0 0XB _ _ _ _0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB _ _ _ _ _ _ _0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 0 XXB 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 _ 0 0 0 _ _1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B
H H H H H H H H H H H H H H H H H H H H H H H H H H H H H
Serial IO
External Interrupt
A/D Converter
16-bit Programable Pulse Generator 0/1
Reserved
PPG2 operation mode control register PPG3 operation mode control register PPG2 and PPG3 clock select register
16-bit Programable Pulse Generator 2/3
Reserved
PPG4 operation mode control register PPG5 operation mode control register PPG4 and PPG5 clock select register
16-bit Programable Pulse Generator 4/5
Reserved
PPG6 operation mode control register PPG7 operation mode control register PPG6 and PPG7 clock select register
16-bit Programable Pulse Generator 6/7
Reserved
(Continued)
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MB90590 Series
Address 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68
H H H H H H H H H H H H H H H H H H H H H H H H H H
Register
PPG8 operation mode control register PPG9 operation mode controlregister PPG8 and PPG9 clock select register
Abbreviation Access PPGC8 PPGC9 PPG89 PPGCA PPGCB PPGAB TMCSR0 TMCSR0 TMCSR1 TMCSR1 ICS01 ICS23 ICS45 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 SGCR SGCR WTCR WTCR PWC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral 16-bit Programable Pulse Generator 8/9
Initial value 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 _ _ _ _ _ _ 0B 0 0 0 _ _ 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 _ _ 0B
Reserved
PPGA operation mode control register PPGB operation mode control register PPGA and PPGB clock select register
16-bit Programable Pulse Generator A/B
Reserved Timer Control Status 0 Timer Control Status 0 Timer Control Status 1 Timer Control Status 1 Input Captue Control Status 0/1 Input Captue Control Status 2/3 Input Captue Control Status 4/5 Output Compare Control Status 0 Output Compare Control Status 1 Output Compare Control Status 2 Output Compare Control Status 3 Output Compare Control Status 4 Output Compare Control Status 5 Sound Control Sound Control Watch Timer Control Watch Timer Control PWM Control 0 16-bit Reload Timer 0 16-bit Reload Timer 1 Input Capture 0/1 Input Capture 2/3 Input Capture 4/5
Reserved Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 Sound Generator Watch Timer Stepping Motor Controller 0 Stepping Motor Controller 1 Stepping Motor Controller 2 Stepping Motor Controller 3
H
H
Reserved PWM Control 1 PWC1 R/W 0 0 0 0 0 _ _ 0B
H
H
Reserved PWM Control 2 PWC2 R/W 0 0 0 0 0 _ _ 0B
H
H
Reserved PWM Control 3 PWC3 R/W 0 0 0 0 0 _ _ 0B
H
(Continued)
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MB90590 Series
Address 69 to 6C 6D H 6E 6F
H H H
Register Serial IO Prescaler Timer Control ROM Mirror
Abbreviation Access Reserved CDCR TCCS ROMM R/W R/W W Reserved
Peripheral Prescaler (Serial IO) I/O Timer ROM Mirror
Initial value 0 XXX 1 1 1 1B 0 0 0 0 0 0 0 0B XXXXXXX1B
70 to 8F H 90 to 9D H 9E 9F A0 A1 A8 A9
H H H H H
Reserved for CAN Interface 0/1. Refer to section about CAN Controller ROM Correction Control Status Delayed Interrupt/release Low-power Mode Clock Selector Watchdog Control Time Base Timer Control Flash Control Status (MB90F594 only. Otherwise reserved) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 PACSR DIRR LPMCR CKSCR WDTC TBTC R/W R/W R/W R/W Reserved R/W R/W Reserved FMCS R/W Reserved ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Flash Memory 0 0 0 X 0 _ _ 0B Watchdog Timer Time Base Timer XXXXX 1 1 1B 1 - - 0 0 1 0 0B ROM Correction Delayed Interrupt Low Power Controller Low Power Controller 0 0 0 0 0 0 0 0B _ _ _ _ _ _ _ 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
A2 to A7
H H
AA to AD H AE H AF H B0 H B1 H B2 H B3 H B4 H B5 B6 B7 B8 B9 BA BB BC BD BE BF
H H H H H H H H H H H
(Continued)
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MB90590 Series
Address 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 190A 190B 190C 190D 190E 190F 1910 1911 1912 1913 1914 1915 1916 1917
H H H H H H H H H H H H H H H H H H H H H H H H
Register Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H
Abbreviation PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral 16-bit Programable Pulse Generator 0/1
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator 2/3
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator 4/5
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator 6/7
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator 8/9
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator A/B
XXXXXXXXB XXXXXXXXB XXXXXXXXB
1918 to 191F H 1920 1921 1922 1923 1924 1925 1926 1927
H H H H H H H H
Reserved Input Capture 0 Input Capture 0 Input Capture 1 Input Capture 1 Input Capture 2 Input Capture 2 Input Capture 3 Input Capture 3 IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 R R R R R R R R Input Capture 2/3 Input Capture 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
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MB90590 Series
Address 1928 1929 192A 192B 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 193A 193B
H H H H
Register Input Capture 4 Input Capture 4 Input Capture 5 Input Capture 5 Output Compare 0 Output Compare 0 Output Compare 1 Output Compare 1 Output Compare 2 Output Compare 2 Output Compare 3 Output Compare 3 Output Compare 4 Output Compare 4 Output Compare 5 Output Compare 5
H
Abbreviation Access IPCP4 IPCP4 IPCP5 IPCP5 OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 OCCP4 OCCP4 OCCP5 OCCP5 TMR0/ TMRLR0 TMR0/ TMRLR0 TMR1/ TMRLR1 TMR1/ TMRLR1 TCDT TCDT SGFR SGAR SGDR SGTR WTBR WTBR WTBR WTSR R R R R Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved
Peripheral
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Input Capture 4/5
192C to 192F H
H H H H H H H H H H H H
Output Compare 0/1
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Output Compare 2/3
Output Compare 4/5
193C to 193F 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 194A 194B 194C 194D
H
Timer 0/Reload 0 Timer 0/Reload 0 Timer 1/Reload 1 Timer 1/Reload 1 Timer Data Timer Data Frequency Dtata Amplitude Data Decrement Grade Tone Count Sub-second Data Sub-second Data Sub-second Data Second Data
R/W 16-bit Reload Timer 0 R/W R/W 16-bit Reload Timer 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Watch Timer Sound Generator IO Timer
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _ _ _ XXXXXB __000000B
H
H
H
H H H H H H H H H H
(Continued)
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MB90590 Series
(Continued) Address
194E 194F 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 195A 195B 195C 195D 195E 195F
H H H H H H H H H H H H H H H H H H
Register Minute Data Hour Data PWM1 Compare 0 PWM2 Compare 0 PWM1 Select 0 PWM2 Select 0 PWM1 Compare 1 PWM2 Compare 1 PWM1 Select 1 PWM2 Select 1 PWM1 Compare 2 PWM2 Compare 2 PWM1 Select 2 PWM2 Select 2 PWM1 Compare 3 PWM2 Compare 3 PWM1 Select 3 PWM2 Select 3
Abbreviation WTMR WTHR PWC10 PWC20 PWS10 PWS20 PWC11 PWC21 PWS11 PWS21 PWC12 PWC22 PWS12 PWS22 PWC13 PWC23 PWS13 PWS23
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral Watch Timer
Initial value __000000B ___00000B XXXXXXXXB XXXXXXXXB __000000B _0000000B XXXXXXXXB XXXXXXXXB __000000B _0000000B XXXXXXXXB XXXXXXXXB __000000B _0000000B XXXXXXXXB XXXXXXXXB __000000B _0 0 0 0 0 0 0 B
Stepping Motor Controller 0
Stepping Motor Controller 1
Stepping Motor Controller 2
Stepping Motor Controller 3
1960 to 19FF H 1A00 to 1AFF H 1B00 to 1BFF H 1C00 to 1CFF H 1D00 to 1DFF H 1E00 to 1EFF H 1FF0 1FF1 1FF2 1FF3 1FF4 1FF5
H H H H H H
Reserved Reserved for CAN Interface 0. Refer to section about CAN Controller Reserved for CAN Interface 1. Refer to section about CAN Controller Reserved for CAN Interface 0. Refer to section about CAN Controller Reserved for CAN Interface 1. Refer to section about CAN Controller Reserved ROM Correction Address 0 ROM Correction Address 1 ROM Correction Address 2 ROM Correction Address 3 ROM Correction Address 4 ROM Correction Address 5 PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 Reserved R/W R/W R/W R/W R/W R/W ROM Correction XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B XXXXXXXX B
1FF6 to 1FFF H Note
Initial value of "_" represents unused bit, "X" represents unknown valu Addresses in the rage 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results reading "X" and any write access should not be performed.
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MB90590 Series
s CAN CONTROLLERS
The CAN controller has the following features: * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmitting of data frames by receiving remote frames * 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz) List of Control Registers Address CAN0 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B
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MB90590 Series
List of Control Registers Address CAN0 001C00H 001C01H 001C02H 001C03H 001C04H 001C05H 001C06H 001C07H 001C08H 001C09H CAN1 001D00H 001D01H 001D02H 001D03H 001D04H 001D05H 001D06H 001D07H 001D08H 001D09H Register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation Access CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER R/W, R R/W R R/W R/W R/W R/W R/W Initial Value 00---000 0----0-1B -------- 000-0000B 00000000 00000000B -1111111 11111111B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXXB
001C0AH 001D0AH 001C0BH 001D0BH 001C0CH 001D0CH 001C0DH 001D0DH 001C0EH 001D0EH 001C0FH 001C10H 001C11H 001C12H 001C13H 001C14H 001C15H 001C16H 001C17H 001C18H 001C19H 001D0FH 001D10H 001D11H 001D12H 001D13H 001D14H 001D15H 001D16H 001D17H 001D18H 001D19H
001C1AH 001D1AH 001C1BH 001D1BH
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MB90590 Series
List of Message Buffers (ID Registers) Address CAN0 001A20H 001A21H 001A22H 001A23H 001A24H 001A25H 001A26H 001A27H 001A28H 001A29H 001A2AH 001A2BH 001A2CH 001A2DH 001A2EH 001A2FH 001A30H 001A31H 001A32H 001A33H 001A34H 001A35H 001A36H 001A37H 001A38H 001A39H 001A3AH 001A3BH 001A3CH 001A3DH 001A3EH 001A3FH CAN1 001B20H 001B21H 001B22H 001B23H 001B24H 001B25H 001B26H 001B27H 001B28H 001B29H 001B2AH 001B2BH 001B2CH 001B2DH 001B2EH 001B2FH 001B30H 001B31H 001B32H 001B33H 001B34H 001B35H 001B36H 001B37H 001B38H 001B39H 001B3AH 001B3BH 001B3CH 001B3DH 001B3EH 001B3FH ID register 7 IDR7 R/W XXXXX--- XXXXXXXXB ID register 6 IDR6 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 5 IDR5 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXXB
(Continued)
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MB90590 Series
(Continued) Address
CAN0 001A40H 001A41H 001A42H 001A43FH 001A44H 001A45H 001A46H 001A47H 001A48H 001A49H 001A4AH 001A4BH 001A4CH 001A4DH 001A4EH 001A4FH 001A50H 001A51H 001A52H 001A53H 001A54H 001A55H 001A56H 001A57H 001A58H 001A59H 001A5AH 001A5BH 001A5CH 001A5DH 001A5EH 001A5FH CAN1 001B40H 001B41H 001B42H 001B43H 001B44H 001B45H 001B46H 001B47H 001B48H 001B49H 001B4AH 001B4BH 001B4CH 001B4DH 001B4EH 001B4FH 001B50H 001B51H 001B52H 001B53H 001B54H 001B55H 001B56H 001B57H 001B58H 001B59H 001B5AH 001B5BH 001B5CH 001B5DH 001B5EH 001B5FH ID register 15 IDR15 R/W XXXXX--- XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 8 IDR8 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
Register
Abbreviation
Access
Initial Value XXXXXXXX XXXXXXXXB
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MB90590 Series
List of Message Buffers (DLC Registers and Data Registers) Address CAN0 001A60H 001A61H 001A62H 001A63H 001A64H 001A65H 001A66H 001A67H 001A68H 001A69H 001A6AH 001A6BH 001A6CH 001A6DH 001A6EH 001A6FH 001A70H 001A71H 001A72H 001A73H 001A74H 001A75H 001A76H 001A77H 001A78H 001A79H 001A7AH 001A7BH 001A7CH 001A7DH 001A7EH 001A7FH 001A80H to 001A87H CAN1 001B60H 001B61H 001B62H 001B63H 001B64H 001B65H 001B66H 001B67H 001B68H 001B69H 001B6AH 001B6BH 001B6CH 001B6DH 001B6EH 001B6FH 001B70H 001B71H 001B72H 001B73H 001B74H 001B75H 001B76H 001B77H 001B78H 001B79H 001B7AH 001B7BH 001B7CH 001B7DH 001B7EH 001B7FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXX ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB XXXXXXXXB to XXXXXXXXB
001B80H to Data register 0 (8 bytes) 001B87H
DTR0
R/W
(Continued)
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(Continued) Address
CAN0 001A88H to 001A8FH 001A90H to 001A97H 001A98H to 001A9FH 001AA0H to 001AA7H 001AA8H to 001AAFH 001AB0H to 001AB7H 001AB8H to 001ABFH 001AC0H to 001AC7H 001AC8H to 001ACFH 001AD0H to 001AD7H 001AD8H to 001ADFH 001AE0H to 001AE7H 001AE8H to 001AEFH 001AF0H to 001AF7H 001AF8H to 001AFFH 28 CAN1
Register
Abbreviation
Access
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
001B88H to Data register 1 (8 bytes) 001B8FH 001B90H to Data register 2 (8 bytes) 001B97H 001B98H to Data register 3 (8 bytes) 001B9FH 001BA0H to Data register 4 (8 bytes) 001BA7H 001BA8H to Data register 5 (8 bytes) 001BAFH 001BB0H to Data register 6 (8 bytes) 001BB7H 001BB8H to Data register 7 (8 bytes) 001BBFH 001BC0H to Data register 8 (8 bytes) 001BC7H 001BC8H to Data register 9 (8 bytes) 001BCFH 001BD0H to Data register 10 (8 bytes) 001BD7H 001BD8H to Data register 11 (8 bytes) 001BDFH 001BE0H to Data register 12 (8 bytes) 001BE7H 001BE8H to Data register 13 (8 bytes) 001BEFH 001BF0H to Data register 14 (8 bytes) 001BF7H 001BF8H to Data register 15 (8 bytes) 001BFFH
DTR1
R/W
DTR2
R/W
DTR3
R/W
DTR4
R/W
DTR5
R/W
DTR6
R/W
DTR7
R/W
DTR8
R/W
DTR9
R/W
DTR10
R/W
DTR11
R/W
DTR12
R/W
DTR13
R/W
DTR14
R/W
DTR15
R/W
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MB90590 Series
s INTERRUPT MAP
Interrupt cause Reset INT9 instruction Exception Time Base Timer External Interrupt (INT0 to INT7) CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS PPG 0/1 PPG 2/3 PPG 4/5 PPG 6/7 PPG 8/9 PPG A/B 16-bit Reload Timer 0 16-bit Reload Timer 1 Input Capture 0/1 Output compare 0/1 Input Capture 2/3 Output Compare 2/3 Input Capture 4/5 Output Compare 4/5 A/D Converter I/O Timer/Watch Timer Serial I/O Sound Generator UART 0 RX UART 0 TX UART 1 RX UART 1 TX UART 2 RX UART 2 TX Flash Memory Delayed interrupt I2OS clear N/A N/A N/A N/A *1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A *1 *1 *1 *1 *1 *1 *1 *1 *1 N/A *1 N/A *2 *1 *2 *1 *2 *1 N/A N/A Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 29
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MB90590 Series
*1: The interrupt request flag is cleared by the I2OS interrupt clear signal. *2: The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available. N/A:The interrupt request flag is not cleared by the I2OS interrupt clear signal. Note: For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the I2OS interrupt clear signal. Note: At the end of IIOS, the IIOS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the IIOS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the IIOS clear signal caused by the first event. So it is recommended not to use the IIOS for this interrupt number. Note: If IIOS is enabled, IIOS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same IIOS Descriptor which should be unique for each interrupt source.. For this reason, when one interrupt source uses the IIOS, the other interrupt should be disabled.
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MB90590 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0 V) Parameter Symbol VCC AVCC AVR DVCC VI VO ICLAMP IOL1 IOLAV1 IOL2
IOLAV2 IOL1 IOL2 IOLAV1 IOLAV2 IOH1 IOHAV1 IOH2 IOHAV2 IOH1 IOH2 IOHAV1 IOHAV2 PD TA TSTG
Power supply voltage
Input voltage Output voltage Clamp Current "L" level max. output current "L" level avg. output current "L" level max. output current "L" level avg. output current "L" level max. overall output current "L" level max. overall output current "L" level avg. overall output current "L" level avg. overall output current "H" level max. output current "H" level avg. output current "H" level max. output current "H" level avg. output current "H" level max. overall output current "H" level max. overall output current "H" level avg. overall output current "H" level avg. overall output current Power consumption Operating temperature Storage temperature
Value Units Remarks Min. Max. VSS - 0.3 VSS + 6.0 V VSS - 0.3 VSS + 6.0 V VCC = AVCC VSS - 0.3 VSS + 6.0 V AVCC AVR, AVR+ AVR - VSS - 0.3 VSS + 6.0 V VCC DVCC VSS - 0.3 VSS + 6.0 V VSS - 0.3 VSS + 6.0 V -2.0 2.0 mA -- 15 mA Normal outputs -- 4 mA Normal outputs, average value -- 40 mA High current outputs -- 30 mA High current outputs, average value -- 100 330 -- 50 250 -- -- -- -- -- -- -- -- -- -- -40 -55 -15 -4 -40 -30 -100 -330 -50 -250 500 400 +85 +150 mA mA mA mA mA mA mA mA mA mA mA mA Sum of all normal outputs Sum of all high current outputs
*1
*2 *2
Sum of all normal outputs, average value Sum of all high current outputs, average value Normal outputs Normal outputs, average value High current outputs High current outputs, average value Sum of all normal outputs Sum of all high current outputs Sum of all normal outputs, average value
Sum of all high current outputs, average value mW MB90F594A, MB90F591 mW MB90594, MB90591 C C
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI rating.
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2. Recommended Conditions
(VSS = AVSS = 0 V) Parameter Power supply voltage Input H voltage Input L voltage Symbol VCC AVCC VIHS VIHM VILS VILM Rated Value Min. 4.5 3V 0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 Typ. 5.0 Max. 5.5 5.5 VCC +0.3 VCC +0.3 0.6VCC VSS + 0.3 Units V V V V V V F C Remarks Under normal operation Maintains RAM data in stop mode CMOS hysteresis input pin MD input pin CMOS hysteresis input pin MD input pin Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor.
Smooth capacitor
CS
0.022
0.1
1.0
Operating temperature
TA
-40
+85
* C Pin Connection Diagram
C CS
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MB90590 Series
3. DC Characteristics
Parameter Output H voltage Output H voltage Output L voltage Output L voltage Input leak current Analog input leak current Symbol VOH1 Pin Normal outputs High current outputs Normal outputs High current outputs (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Rated Value Test Condition Units Remarks Min. Typ. Max. VCC = 4.5 V, IOH1 = -4.0 mA VCC = 4.5 V, IOH2 = -30.0 mA VCC = 4.5 V, IOL1 = 4.0 mA VCC = 4.5 V, IOL2 = 30.0 mA VCC = 5.5 V, VSS < VI < VCC AN0 to AN7 VCC = 5.5 V, AVSS < VI < AVCC VCC = 5.0 V10%, Internal frequency: 16 MHz, At normal operation. VCC = 5.0 V10%, Internal frequency: 16 MHz, At Sleep mode. VCC ICTS VCC = 5.0 V1%, Internal frequency: 2 MHz, At Timer mode VCC - 0.5 -- -- V
VOH2
VCC - 0.5
--
--
V
VOL1
--
--
0.4
V
VOL2
--
--
0.5
V A A mA mA mA mA mA mA mA mA mA mA mA mA A A A A MB90594 MB90F594A MB90F591 MB90591 MB90594 MB90F594A MB90F591 MB90591 MB90594 MB90F594A MB90F591 MB90591 MB90594 MB90F594A MB90F591 MB90591
IIL IIAL
-5 -1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- 37 50 TBD TBD 13 15 TBD TBD 0.3 0.35 TBD TBD 5 5 TBD TBD
5 1 60 80 TBD TBD 20 23 TBD TBD 0.6 0.6 TBD TBD 20 20 TBD TBD
ICC
ICCS Power supply current *
ICCH
VCC = 5.0 V10%, At Stop mode, TA = 25C Other than C, AVCC, AVSS, AVR+, AVR-, VCC, VSS, DVCC, DVSS
Input capacity
CIN
--
--
10
80
pF
*: Current values are tentative. They are subject to change without notice according to improvements in the characteristics. The power supply current testing conditions are when using the external clock. 33
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MB90590 Series
4. AC Characteristics
(1) Clock Timing (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Units Remarks Min. Typ. Max. 3 62.5 -- 10 -- 1.5 62.5 -- -- -- -- -- -- -- 16 333 5 -- 5 16 666 MHz ns % ns ns MHz ns Duty ratio is about 30 to 70%. When using external clock
Parameter Oscillation frequency Oscillation cycle time Frequency deviation with PLL * Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time
Symbol fC tCYL f PWH, PWL tCR, tCF fCP tCP
Pin X0, X1 X0, X1 -- X0 X0 -- --
*: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock. f = ----- x 100% fo
+ Central frequency fO -
* Clock Timing tHCYL 0.8 VCC X0 PWH tCF PWL tCR 0.2 VCC
Example of Oscillation circuit
Make
X0 X1
Oscillator TBD
Frequency (MHz) 4MHz
C1 (pF) TBD
C2 (pF) TBD
R () TBD
TBD
R
C1
C2
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MB90590 Series
* Guaranteed operation range Guaranteed operation range 5.5 4.5 Power supply voltage VCC (V) 3.0
TBD
Guaranteed PLL operation range
1.5
8 Machine clock fCP (MHz)
16
* Ocsillation clock frequency and Machine clock frequency x4 x3 x2 x1
16 12 Machine clock fCP (MHz) 9 8
x1/2 (PLL off)
4
3
4
8 Oscillation clock fC (MHz)
16
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MB90590 Series
(2) Reset and Hardware Standby Input (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Rated Value Pin Units Remarks Min. Max. RST 16 tCP -- ns
Parameter Reset input time
Symbol tRSTL
Hardware standby input time tHSTL HST 16 tCP -- ns "tcp" represents one cycle time of the machine clock. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
tRSTL, tHSTL RST HST
0.6 VCC
0.6 VCC
(3) Power On Reset
Parameter Power on rise time Power off time
Symbol tR tOFF
Pin VCC VCC
(VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85) Rated Value Test Condition Units Remarks Min. Max. -- 0.05 50 30 -- ms ms Due to repetitive operation
tR
VCC 0.2 V
3.5 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 mV/sec, you can operate while using the PLL clock. 0.2 V
VCC 3V Holds RAM data VSS We recommend a rise of 50 mV/ms maximum.
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(4) UART0/1/2, Serial I/O Timing (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Pin Symbol Condition Units Remarks Min. Max. SCK0 to SCK3 SCK0 to SCK3, SOT0 to SOT3 Internal clock operaSCK0 to SCK3, tion output pins are CL = 80 pF + 1 TTL. SIN0 to SIN3 SCK0 to SCK3, SIN0 to SIN3 SCK0 to SCK3 SCK0 to SCK3 SCK0 to SCK3, External clock operSOT0 to SOT3 ation output pins are SCK0 to SCK3, CL = 80 pF + 1 TTL. SIN0 to SIN3 SCK0 to SCK3, SIN0 to SIN3 8 tCP -80 100 60 4 tCP 4 tCP -- 60 60 -- 80 -- -- -- -- 150 -- -- ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Note:
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
1. AC characteristic in CLK synchronized mode. 2. CL is load capacity value of pins when testing. 3. tCP is the machine cycle (Unit: ns). * Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.6 VCC tSHIX 0.8 VCC 0.6 VCC 0.8 V
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MB90590 Series
* External Shift Clock Mode tSLSH SCK 0.6 VCC 0.6 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.6 VCC tSHIX 0.8 VCC 0.6 VCC tSHSL 0.8 VCC 0.8 VCC
(5)Timer Related Resource Input Timing
Parameter Input pulse width
Symbol tTIWH tTIWL
Pin TIN0 IN0 to IN5
(VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. -- 4 tCP -- ns
* Timer Input Timing
0.8 VCC tTIWH
0.8 VCC 0.6 VCC tTIWL 0.6 VCC
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MB90590 Series
(6)Trigger Input Timing (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Pin INT0 to INT7, ADTG Condition -- Value Min. 5 tCP Max. -- Units ns Remarks
Parameter Input pulse width
Symbol tTRGH tTRGL
* Trigger Input Timing
0.8 VCC tTRGH
0.8 VCC 0.6 VCC tTRGL 0.6 VCC
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MB90590 Series
5. A/D Converter
( VCC = AVCC = 5.0 V10%, VSS = AVSS = 0 V,3.0 V AVR+ - AVR-, TA = -40 C to +85 C) Symbol -- -- -- -- VOT VFST -- -- IAIN VAIN -- -- IA IAH IR IRH -- Pin -- -- -- -- Value Min. -- -- -- -- -- -- -- Typ. Max. 10 5.0 2.5 1.9 Units Remarks bit LSB LSB LSB mV mV ns ns A V V V mA A A A LSB *1 *1
Parameter Resolution Conversion error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Conversion time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage current Offset between input channels
AN0 to AN7 AVR- - 3.5 AVR- +0.5 AVR- + 4.5 AN0 to AN7 AVR+ - 6.5 AVR+ -1.5 AVR+ + 1.5 -- -- AN0 to AN7 AN0 to AN7 AVR+ AVRAVCC AVCC AVR+ AVR+ AN0 to AN7 -- -- -1 AVRAVR- + 2.7 0 -- -- 200 -- -- 352tCP 64tCP -- -- -- -- 5 -- 400 -- -- -- -- +1 AVR+ AVCC AVR+ - 2.7 -- 5 600 5 4
*1: When not operating A/D converter, this is the current (VCC = AVCC = AVR+ = 5.0 V) when the CPU is stopped.
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MB90590 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error 3FF 3FE 3FD Actual conversion value 0.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
Digital output
004 003 002 001
VNT (mesured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVR - Analog input AVR + VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB
1 LSB = (Theoretical value)
AVR + - AVR - 1024
[V]
Total error for digital output N =
[LSB]
VOT (Theoretical value) = AVR - + 0.5 LSB[V] VFST (Theoretical value) = AVR + - 1.5 LSB[V]
VNT: Voltage at a transition of digital output from (N - 1) to N
(Continued)
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MB90590 Series
(Continued)
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x (N - 1)+ VOT} VFST (mesured value) N+1 Actual conversion value Differential linearity error Theoretical characteristics
Digital output
Digital output
N
VNT 004 003 002 001 Theoretical characteristics VOT (mesured value) AVR - Analog input AVR + Actual conversion characteristics
N-1
V(N + 1)T (mesured value) VNT (mesured value)
N-2
Actual conversion value
AVR -
Analog input
AVR +
VNT - {1 LSB x (N - 1) + VOT} Linearity error of [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = VFST - VOT V(N + 1)T - VNT 1 LSB - 1 LSB [LSB]
[V] 1022 VOT: Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH"
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 15 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Equipment of analog input circuit model
Analog input C0 Comparator C1
Note: Listed values must be considered as standards. * Error The smaller the | AVR + - AVR - |, the greater the error would become relatively. 42
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MB90590 Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning
Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. * Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles. 43
I S T N Z V C RMW
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MB90590 Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst
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Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension *
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note : The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
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Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Listed in tables of instructions 1 2 1 1 2 2 0 0
Note : "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) (b) byte
Cycles Access
(c) word
Cycles Access
(d) long
Cycles Access
+0 +0 +0 +1 +1 +1
1 1 1 1 1 1
+0 +0 +2 +1 +4 +4
1 1 2 1 2 2
+0 +0 +4 +2 +8 +8
2 2 4 2 4 4
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
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Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # ~ Transfer Instructions (Byte) [41 Instructions]
RG
B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b)
Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LH AH
I
S
T
N
Z
V
C
RMW
3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
Z Z Z Z Z Z Z Z Z Z
* * * * * * * - * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
X* X* X* X* X* X* X* X- X* X* - - - - - - - - - - - - - - - - - Z Z - - - - - - - - - - - - - - - - - - - - - - -
4 2 2+ 5+ (a) 7 2 2+ 9+ (a)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 # Transfer Instructions (Word/Long Word) [38 Instructions] ~
RG
B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c)
Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16
LH AH
I
S
T
N
Z
V
C
RMW
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0
- - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) - - - - - - - - - -
* * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW dir, A MOVW addr16, A MOVW SP A , MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 4 2+ 5+ (a) 2 7 2+ 9+ (a) 2 4 2+ 5+ (a) 5 3 2 4 2+ 5+ (a)
2 0 0 2x (c) 4 0 2 2x (c) 2 0 0 2 0 0 (d) 0 0 (d)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
RG
B 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0
Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C)
LH AH
I
S
T
N
Z
V
C
RMW
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
Z Z Z Z - Z Z Z Z byte (A) (AH) + (AL) + (C) (decimal) Z Z byte (A) (A) -imm8 Z byte (A) (A) - (dir) Z byte (A) (A) - (ear) Z byte (A) (A) - (eam) - byte (ear) (ear) - (A) - byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) Z byte (A) (A) - (ear) - (C) Z byte (A) (A) - (eam) - (C) Z byte (A) (AH) - (AL) - (C) (decimal) Z word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL
A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2 2 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 7 2+ 9+ (a) 2 7 2+ 9+ (a)
2 0 2 0 2 0 2 0 4 0 4 0
0 byte (ear) (ear) +1 2x (b) byte (eam) (eam) +1 0 byte (ear) (ear) -1 2x (b) byte (eam) (eam) -1 0 word (ear) (ear) +1 2x (c) word (eam) (eam) +1 0 word (ear) (ear) -1 2x (c) word (eam) (eam) -1 0 long (ear) (ear) +1 2x (d) long (eam) (eam) +1 0 long (ear) (ear) -1 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # 1 2 2+ 2 Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 0 0 1 0 0 2 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
A 1 A, ear 2 A, eam 2+ A, #imm16 3 A, ear 2 A, eam 2+ A, #imm32 5
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ *
1
RG
B
Operation
Quotient byte (AL) Remainder byte (AH) Quotient byte (A) Remainder byte (ear) Quotient byte (A) Remainder byte (eam) Quotient word (A) Remainder word (ear) Quotient word (A) Remainder word (ear)
LH AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
0 word (AH) /byte (AL) 0 word (A)/byte (ear)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
*2
A, eam 2+ *3 2 *4
*6 word (A)/byte (eam) 0 long (A)/word (ear)
DIVUW A, ear
DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10
*7 long (A)/word (eam)
0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A)
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 2 2 ~ *1 *2 *3 *4 *5
RG
Mnemonic DIV DIV DIV DIVW DIVW A A, ear
B 0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
A, eam 2 + A, ear A, eam 2 2+
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A)
Z Z Z - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
* * * * *
* * * * *
- - - - -
MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4:
A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 +
*8 *9 *10 *11 *12 *13
0 1 0 0 1 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
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Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b)
Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A)
LH AH
I
S
T
N
Z
V
C
RMW
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
0 byte (A) not (A) 0 byte (ear) not (ear) 2x (b) byte (eam) not (eam) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
0 word (A) not (A) 0 word (ear) not (ear) 2x (c) word (eam) not (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a) Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
2 0 2 0 2 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A)
LH
AH
I
S
T
N
Z
V
C
RMW
0 2 0 0 2 0
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - * - - *
2 3 2+ 5+ (a) 1 2
0 byte (ear) 0 - (ear) 2x (b) byte (eam) 0 - (eam) 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2+ 5+ (a)
0 word (ear) 0 - (ear) 2x (c) word (eam) 0 - (eam)
Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 B 0
Normalize Instruction (Long Word) [1 Instruction] Operation
LH AH I S T N Z V C RMW
long (A) Shift until first digit is "1" - byte (R0) Current shift count
-
-
-
-
-
*
-
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 18 Mnemonic
RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
# 2 2
~ 2 2
B 0 0
Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit)
LH AH
I
S
T
N
Z
V
C
RMW
0 0
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
--- --- - - - - - - - - - - - -
* * * * * * * * *
* * * * * * * * *
- - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * *
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
--* --* ---
ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit)
word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
--*** --*R* ---** --* --* --- --* --* --- * * * * * * * * * * * *
long (A) Arithmetic right shift (A, R0) -
- -
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10
1
Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0
LH AH I S T N Z V C RMW
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24
word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2)
2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6
(c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c)
CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7:
2+ 11+ (a) 4 10
word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE
CBNE
Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH I S T N Z V C RMW
# 3 4
10
~ * *1 *2 *3 *4 *3 *5
1
RG
0 0 1 0 1 0 2
- - - - - - - - - - - - - - - -
----* ----* - - - - - - - - - - - - - - - - * * * *
* * * * * * * * * * - - - - *
* * * * * *
* * * * * *
- - - - - - - * - * - - - - - -
ear, #imm8, rel
eam, #imm8, rel*
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
4 4+ 5 5+ 3
DBNZ DBNZ
ear, rel eam, rel
3+ *6 3 *5
Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 2 0 0 0 0 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
----* ----* ----* ----* - - - - - R R R R * S S S S * - - - - * - - - - *
*- *- *- *- - - - - * - - - - *
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
#local8
--------
UNLINK RET *8 RETP *9
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
-------- -------- --------
- - -
*1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 21 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2
RG
B (c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LH AH
I
S
T
N
Z
V
C
RMW
0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
- - - - - - - - -
- - - - * - - - - - - - - - - * * - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
------- ------- ******* ------- * * * * * * * * * * * * * * * * * * * * *
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AND CCR, #imm8 OR CCR, #imm8 MOV RP #imm8 , MOV ILM, #imm8
byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation
Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space
- - - - - - - -
------- ------- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
------- ------- --- --- - - - - - - - - - - - - - - - - - - - - - * * - - - - - - - * * - - - - - - - -- -- - - - - - - - - - - - - - -
Z* -- - - - - - - - - - - - - - -
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH I S T N Z V C RMW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *5 *5 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 23 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1
RG
B 0 0 0 0 0 0
Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
0 0 0 0 0 0
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
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Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1
2
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
RG
B * *3 *4 *4 *3 *6 *6 *7 *7 *6
3
* *5 *5 *5
5
Byte transfer @AH+ @AL+, counter = RW0 Byte transfer @AH- @AL-, counter = RW0 Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 Word transfer @AH+ @AL+, counter = RW0 Word transfer @AH- @AL-, counter = RW0 Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8
MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 2
2 6m +6 *8
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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MB90590 Series
s ORDERING INFORMATION
Part number MB90549PF MB90591PF MB90F594APF MB90591PF MB90V590ACR Package 100-pin Plastic QFP (FPT-100P-M06) 256-pin Ceramic PGA (PGA-256C-A01) Remarks
For evaluation
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MB90590 Series
s PACKAGE DIMENSION
100-pin plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
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MB90590 Series
250-pin ceramic PGA (PGA-256-A01)
C0.51 (.020) TYP (3 PLCS)
0.20 0.05 (.0079 .002)
22.86 (.900) REF
INDEX AREA C1.02 (.040) TYP 25.10 0.30 SQ (.988 .012) 6.35 (.250) MAX
1.27 (.050) TYP 1.50 + 0.30 (.059 + .012 ) - 0.10 - .004 EXTRA INDEX PIN
C
1994 FUJITSU LIMITED R256001SC-5-3
Dimensions in mm (inches)
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MB90590 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9909 (c) FUJITSU LIMITED Printed in Japan

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